In a conventional design flow, all customer designed logic is treated in the same way (i.e., the customer designed logic is operated on as raw RTL). The customer cannot package parts of the customer's design into re-usable intellectual property (IP). Subsequent customer designs that reuse logic from a prior customer design still require the entire customer designed logic to be entered into the design system from scratch. Conventional tools do not provide for re-use of the effort from an initial design, in subsequent designs. For example, if the customer has customer designed IP that is to be reused, each time the customer designed IP is reused, the customer has to go through all the stages of an implementation flow.
Re-running all of the stages of the implementation flow, on all logic for subsequent designs that share IP is inefficient, is time consuming and can be frustrating to the customer. Also, design-timing closure can be complicated and have a long run time during design placement and optimization.
It would be desirable to have a method and/or apparatus enabling efficient design reuse in platform/structured ASICs.